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[Other resource] FIRvhdl

Description: 用vhdl实现一个fir滤波器设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

[Other resource] fir_filter

Description: 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Platform: | Size: 2996 | Author: li | Hits:

[Other resource] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152436 | Author: 冯申 | Hits:

[Other resource] FIR_vhdl

Description: 基本FIR滤波器的VHDL源代码及其测试程序。-basic FIR filter VHDL source code and testing procedures.
Platform: | Size: 1441 | Author: qjyong | Hits:

[Technology Management] FIR_poroje

Description: this project is about FIR FIlter By VHdl codes in the ISE.
Platform: | Size: 2798592 | Author: Atefeh | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 用VHDL语言写的FIR滤波器，简单易懂，拿来直接用，10节窗函数法带通滤波器-Write VHDL FIR filter, easy to understand, be used directly, 10 bandpass filter window function method
Platform: | Size: 88064 | Author: Mr 致圆彭 | Hits:

[VHDL-FPGA-Verilog] fir_lms-adaptive-filter

Description: 采用VHDL语言编写的fir级联结构的LMS自适应滤波器，方便学习研究自适应滤波器有关参数实际实现的影响-Using VHDL language fir cascade structure of LMS adaptive filter, adaptive filter to facilitate study and research the impact of the actual implementation of the relevant parameters
Platform: | Size: 2563072 | Author: 朱岩 | Hits:

[VHDL-FPGA-Verilog] FIR-FILTER

Description: FIR filter LUT based in vhdl
Platform: | Size: 217088 | Author: sat | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 用VHDL写的FIR滤波器，前端有DDS产生波源-Write VHDL FIR filter, front end DDS generated wave source
Platform: | Size: 5413888 | Author: huag | Hits:

[Software Engineering] 1.High-Speed-FPGA-Implementation-of-FIR-Filter-fo

Description: related to VHDL language project
Platform: | Size: 10240 | Author: Bhushan | Hits:

[LabView] Ref-exstfir-VHDL-Code

Description: code for an fir filter of n length order with different multipliers and adders
Platform: | Size: 29696 | Author: Dwarakanadh | Hits:

[VHDL-FPGA-Verilog] Low-Power-FIR-Filter

Description: FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
Platform: | Size: 437248 | Author: 金铁男 | Hits:

[VHDL-FPGA-Verilog] fir_noRom

Description: 有VHDL实现对复杂信号的16位fir滤波器-desgin the 16 bits FIR Filter by VHDL
Platform: | Size: 5129216 | Author: 林嘉英 | Hits:

[Other] filter

Description: 此程序是一个用VHDL语言编写的fir滤波器。经过了仿真验证，很好用。-This procedure is a VHDL language fir filter. After the simulation, very good use.
Platform: | Size: 74752 | Author: 李振宇 | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL. FIR 滤波器声音处理。 I2C configuration inerface, -VHDL. FIR filter sound processing. I2C configuration inerface,
Platform: | Size: 6144 | Author: 水彬 | Hits:

[VHDL-FPGA-Verilog] fpga-fir

Description: 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog language
Platform: | Size: 1404928 | Author: 韩闯 | Hits:

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[Other resource] FIRvhdl

[Other resource] fir_filter

[Other resource] FPGA_FIR

[Other resource] FIR_vhdl

[Technology Management] FIR_poroje

[VHDL-FPGA-Verilog] FIR

[VHDL-FPGA-Verilog] fir_lms-adaptive-filter

[VHDL-FPGA-Verilog] FIR-FILTER

[VHDL-FPGA-Verilog] FIR

[Software Engineering] 1.High-Speed-FPGA-Implementation-of-FIR-Filter-fo

[LabView] Ref-exstfir-VHDL-Code

[VHDL-FPGA-Verilog] Low-Power-FIR-Filter

[VHDL-FPGA-Verilog] fir_noRom

[Other] filter

[Embeded-SCM Develop] VHDL

[VHDL-FPGA-Verilog] fpga-fir

[VHDL-FPGA-Verilog] FIR

[Other] New-Text-Document.bmp

[Other] E4_6_FirIpCore

[VHDL-FPGA-Verilog] Rawski

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